一种用于自适应直方图均衡化的硬件加速器

doi:10.12066/j.issn.1007-2861.2044

Abstract

Abstract:

In order to solve the problem that the dynamic histogram equalization (DHE) algorithm does not work well and that the algorithm cannot be applied flexibly, a field programmable gate array (FPGA)-based hardware accelerator design method for improved adaptive histogram equalization algorithm is proposed. The hardware accelerator improves the histogram equalization algorithm and adaptively limits the contrast stretch. It is designed in modularity after taking full advantage of the parallel architecture and abundant block storage resources that FPGA has. Experiment results show that the improved algorithm does not result in excessive enhancement, noise amplification and loss of image detail. The proposed hardware accelerator not only performs well in saving hardware resources but is effective as well in practical application. In real-time image processing, it takes only about 0.1 milliseconds for the processing of a frame image, thus making the image enhancement algorithm in real-time image processing more easily accessible.

Key words: field programmable gate array (FPGA), adaptive, histogram, hardware accelerator

CLC Number:

TP391

LU Shenyang, RAN Feng, GUO Aiying, SHEN Huaming. A hardware accelerator for adaptive histogram equalization[J]. Journal of Shanghai University（Natural Science Edition）, 2020, 26(3): 401-412.

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A hardware accelerator for adaptive histogram equalization

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