关键词: 同步动态随机读写存储器, 训练, 延迟电路, 自适应

Abstract: Memory is a core device in system on a chip (SoC) and other electronic systems for data exchange and storage at different levels. However, memory access errors may occur due to factors such as raise of frequency, jitter, phase drift, unreasonable placement and routing. An adaptive synchronize method focusing on the training of clock signal is designed for synchronous dynamic random access memory (SDRAM) interface to enhance stability of memory access. A CPU-controlled delay circuit is used to shift the phase of SDRAM clock signal. A training program is designed to cooperate with the delay module hardware for memory interface tuning. In the training mode, CPU writes test data to the memory and reads them back, judging whether they are matching or not. Training program tunes the delay circuit according to the test results. A valid data sampling window is obtained rapidly and accurately after several iterations. Using the method, the middle of the window is calculated, which is the optimal phase drift for SDRAM clock signal and can improve stability of memory access.

Key words: adaptive, delay circuit, synchronous dynamic random access memory (SDRAM), training