Double filtration test point selection strategy for LBIST

Expand
  • 1. Microelectronic Research and Development Center, Shanghai University, Shanghai 200444, China
    2. Key Laboratory of Special Fiber Optics and Optical Access Networks, Shanghai University, Shanghai 200444, China
    3. Software Research and Development Center, Shanghai Sansi Electronic Engineering Co., Ltd., Shanghai 201199, China

Received date: 2018-06-19

  Online published: 2018-07-03

Abstract

To solve the problem of low fault coverage rate in logic built-in self-test (LBIST) caused by test pattern using pseudorandom vector generator, an easily controlled and easily adjustable insertion technology of testing point has been applied. However, in the test points selection process of test point insertion (TPI), the usual criterion is ''fault coverage rate precedence'', which results in too high area overhead of some test points. To address the issue, a double filtration testing point selection strategy that can be used for LBIST has been proposed through analysis of existing mainstream selection strategies. This method first manages to obtain a single test point set of high fault coverage rate/low area overhead through pre-filtration to safeguard the whole quality of TPI. Next a single test point with high coincidence of fault coverage is filtered through filtration of global test points to complete TPI conforming to the boundary condition. Experimental results indicate that the method proposed in the paper, compared with presently novel compact unit perceived test point selection strategy, has the advantage of enhancing the fault coverage rate by 4.15%, and reducing the area overhead by 5.72%.

Cite this article

DONG Chengliang, ZHANG Jinyi, QING Pei . Double filtration test point selection strategy for LBIST[J]. Journal of Shanghai University, 2020 , 26(4) : 518 -526 . DOI: 10.12066/j.issn.1007-2861.2067

References

[1] LaPedus M. 浅析 7 nm 之后的工艺制程的实现[J]. 集成电路应用, 2017,34(1):50-53.
[2] Gherman V, Wunderlich H J, Vranken H, et al. Efficient pattern mapping for deterministic logic BIST[C]// Proceedings of International Test Conference on International Test Conference. 2004: 48-56.
[3] Sankaralingam R, Touba N A. Inserting test points to control peak power during scan testing[C]// IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2002: 138-146.
[4] Chen M J, Xiang D. Pseudorandom scan BIST using improved test point insertion tech- niques[C]// 7th International Conference on Solid-State and Integrated Circuits Technology. 2004. DOI: 10.1109/ICSICT.2004.1435244.
[5] Milewski S, Mukherjee N, Rajski J, et al. Full-scan LBIST with mcapture-per-cycle hybrid test points[C]// IEEE International Test Conference. 2017. DOI: 10.1109/TEST.2017.8242036.
[6] Acero C, Feltham D, Liu Y, et al. Embedded deterministic test points[J]. IEEE Transactions on Very Large Scale Integration Systems, 2017,99:1-2.
[7] Liu Y D, Moghaddam E, Mukherjee N, et al. Minimal area test points for deterministic patterns[C]// IEEE International Test Conference. 2017. DOI: 0.1109/TEST.2016.7805825.
[8] Acero C, Feltham D, Patyra M, et al. On new test points for compact cell-aware tests[J]. IEEE Design & Test, 2016,33(6):7-14.
[9] He M T, Contreras G K, Tehranipoor M, et al. Test-point insertion efficiency analysis for LBIST applications[C]// IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2016. DOI: 10.1109/VTS.2016.7477314.
[10] Moghaddam E, Mukherjee N, Rajski J, et al. Test point insertion in hybrid test compression/LBIST architectures[C]// IEEE International Test Conference. 2016. DOI: 10.1109/TEST.2016.7805826.
[11] Liang B, Zhang J, Tang D. Fast iterative closest point-simultaneous localization and mapping (ICP-SLAM) with rough alignment and narrowing-scale nearby searching[J]. Journal of Donghua University (English Edition), 2017,34(4):583-590.
[12] Singh A D. Cell aware and stuck-open tests[C]// 21th IEEE European Test Symposium. 2016. DOI: 10.1109/ETS.2016.7519316.
[13] Mukherjee N, Rajski J, Tyszer J. Defect aware to power conscious tests-the new DFT landscape[C]// 22nd International Conference on VLSI Design. 2009. DOI: 10.1109/VLSI.Design.2009.111.
[14] He M T, Contreras G K, Tran D, et al. Test-point insertion efficiency analysis for LBIST in high-assurance applications[J]. IEEE Transactions on Very Large Scale Integration Systems, 2017,99:1-14.
Outlines

/