Abstract: This paper presents a novel method of automatic test pattern generation for multi clock system, called S&CCT. The method classifies the system into equivalent clocks and serial clocks according to some regulations, and fixes the rightness of capture sequence. A concurrent fault simulator is used to simulate test vectors both on logic and timing in ATPG. The test vector generat or uses the simulating information, avoiding generating invalid vectors. Experiments show that S&CCT can reduce the number of test vectors by about 50% comparing with common methods, and has no influence on the cost of circuit hardware.

Key words: automatic test pattern generation (ATPG), data flow chart, test coverage, test protocol, the classification standard of the clocks, safe and complete capture technology (S&CCT)