Abstract: According to the advantages of ternary optical computer such as reconfigurable arithmetic unit, large number of data bits and no-carry-delay MSD adder, a 40-bit multiplication routine is designed and developed. In the routine, the numerical value is expressed with the MSD number system as in a ternary optical computer. Partial products are generated via a three-valued logic transform (M). The product is obtained by summing all partial products through an MSD adder using an iterative method. A fast-calculation method is applied in the M transform, and a pipeline technology used in the MSD adder to accumulate the partial products. The operation steps and simulation experiments of the routine are given in detail, and the performance comparing with electronic computer
analyzed.

Key words: MSD adder, multiplication routine, ternary optical computer