Abstract: Aiming at the problem of long computation time of polynomial multiplication in fully homomorphic encryption (FHE), a hardware multiplication structure is designed to accelerate it. First, the design of the configurable hardware modular addition unit is completed by combining the two hardware modular addition structures. Then Barrett reduction method is improved through the utilization of a special modulus method, which serves to accelerate the modular reduction computation time. The optimized reduction method is then used to improve the optimized constant-geometry number-theoretic transform (CG-NTT) algorithm. At last, complete the design of the multiplication module on a field-programmable gate array (FPGA) platform. The experimental results show that by using the hardware multiplication structure, the polynomial multiplication computation time can be reduced by 96.26% and the resource consumption of look-up-table (LUT) can be reduced by 50.71% to 93.97%.

Key words: fully homomorphic encryption, polynomial multiplication computation, number-theoretic transform