为提高0.35 μm 30_40_50 V BCD (bipolar-CMOS-DMOS)工艺下50 V HVPMOS 的电学性能, 在不改变工艺流程的基础上, 仅通过微调器件结构尺寸来实现电学性能的优化. 采用Silvaco 公司的工艺与器件模拟软件,仿真分析了沟道长度、overlap 尺寸、场氧化层长度及场极板长度对50 V HVPMOS 器件电学性能的影响. 根据仿真结果确定了优化后的结构尺寸, 并结合流片测试结果验证了优化方案的可行性. 测试结果表明, 优化后50 V HVPMOS 的开启电压降低到了–0.98 V, 击穿电压提高到了–68 V, 特征导通电阻降低了13.5%, 饱和电流提高了13.1%, 器件的安全工作范围增大, 饱和区更加平滑, 无明显kink 效应.
This paper aims to improve the electrical properties of 50 V HVPMOS using the 0.35 μm 30_40_50 V BCD (bipolar-CMOS-DMOS) process by adjusting the dimensions of device structure without changing the original process. The process and device simulation of Silvaco Inc. has been used to analyze the influences of the channel length, overlap size, field oxide layer length and field plate length on the electrical properties of 50 V HVPMOS. The optimized dimensions were determined according to the simulation results, and feasibility of the optimization scheme was verified by the result of tape out. The test results show that the threshold voltage reduces to –0.98 V, the breakdown voltage increases to –68 V, the specific on-resistance is reduced by 13.5% and the saturation current is increased by 13.1% after the optimal design. Furthermore, the saturated zone is smoother without obvious kink effect.
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