针对全同态加密(fully homomorphic encryption,FHE)中多项式乘法计算时间较长的问题,设计了1种硬件乘法结构对其进行加速.首先,结合2种硬件模加结构完成可配置的硬件模加单元设计,降低了硬件资源消耗;然后,利用特殊模数法对Barrett约减法进行改进,缩短了模约减计算时间,并将其用于改进优化的常数-几何数论变换(constant-geometrynumber-theoretic transform,CG-NTT)算法;最后,在现场可编程门阵列(field-programmable gate array,FPGA)平台上完成乘法模块设计.实验结果表明,使用硬件乘法结构能够减少96.26%的多项式乘法计算时间,并且查找表(look-up-table,LUT)的资源消耗能够减少50.71%$\sim$93.97%.
Aiming at the problem of long computation time of polynomial multiplication in fully homomorphic encryption (FHE), a hardware multiplication structure is designed to accelerate it. First, the design of the configurable hardware modular addition unit is completed by combining the two hardware modular addition structures. Then Barrett reduction method is improved through the utilization of a special modulus method, which serves to accelerate the modular reduction computation time. The optimized reduction method is then used to improve the optimized constant-geometry number-theoretic transform (CG-NTT) algorithm. At last, complete the design of the multiplication module on a field-programmable gate array (FPGA) platform. The experimental results show that by using the hardware multiplication structure, the polynomial multiplication computation time can be reduced by 96.26% and the resource consumption of look-up-table (LUT) can be reduced by 50.71% to 93.97%.
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