面向全同态加密的多项式乘法的加速设计

doi:10.12066/j.issn.1007-2861.2634

上海大学学报(自然科学版) ›› 2025, Vol. 31 ›› Issue (4): 735-745.doi: 10.12066/j.issn.1007-2861.2634

面向全同态加密的多项式乘法的加速设计

田辉辉¹, 严利民^1,2

1. 上海大学微电子研究与开发中心, 上海 200444;
2. 上海大学机电工程与自动化学院, 上海 200444

收稿日期:2024-06-02 出版日期:2025-08-31 发布日期:2025-09-16
通讯作者: 严利民(1971—),男,副教授,博士,研究方向为集成电路与信息安全. E-mail:yanlm@shu.edu.cn
基金资助:
国家自然科学基金资助项目(52107112)

Accelerated design of polynomial multiplication for fully homomorphic encryption

TIAN Huihui¹, YAN Limin^1,2

1. Microelectronics Research and Development Center, Shanghai University, Shanghai 200444, China;
2. School of Mechatronic Engineering and Automation, Shanghai University, Shanghai 200444, China

Received:2024-06-02 Online:2025-08-31 Published:2025-09-16

摘要/Abstract

摘要： 针对全同态加密(fully homomorphic encryption,FHE)中多项式乘法计算时间较长的问题,设计了1种硬件乘法结构对其进行加速.首先,结合2种硬件模加结构完成可配置的硬件模加单元设计,降低了硬件资源消耗;然后,利用特殊模数法对Barrett约减法进行改进,缩短了模约减计算时间,并将其用于改进优化的常数-几何数论变换(constant-geometrynumber-theoretic transform,CG-NTT)算法;最后,在现场可编程门阵列(field-programmable gate array,FPGA)平台上完成乘法模块设计.实验结果表明,使用硬件乘法结构能够减少96.26%的多项式乘法计算时间,并且查找表(look-up-table,LUT)的资源消耗能够减少50.71%$\sim$93.97%.

关键词: 全同态加密, 多项式乘法计算, 数论变换

Abstract: Aiming at the problem of long computation time of polynomial multiplication in fully homomorphic encryption (FHE), a hardware multiplication structure is designed to accelerate it. First, the design of the configurable hardware modular addition unit is completed by combining the two hardware modular addition structures. Then Barrett reduction method is improved through the utilization of a special modulus method, which serves to accelerate the modular reduction computation time. The optimized reduction method is then used to improve the optimized constant-geometry number-theoretic transform (CG-NTT) algorithm. At last, complete the design of the multiplication module on a field-programmable gate array (FPGA) platform. The experimental results show that by using the hardware multiplication structure, the polynomial multiplication computation time can be reduced by 96.26% and the resource consumption of look-up-table (LUT) can be reduced by 50.71% to 93.97%.

Key words: fully homomorphic encryption, polynomial multiplication computation, number-theoretic transform

中图分类号:

TP309

田辉辉, 严利民. 面向全同态加密的多项式乘法的加速设计[J]. 上海大学学报(自然科学版), 2025, 31(4): 735-745.

TIAN Huihui, YAN Limin. Accelerated design of polynomial multiplication for fully homomorphic encryption[J]. Journal of Shanghai University（Natural Science Edition）, 2025, 31(4): 735-745.

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面向全同态加密的多项式乘法的加速设计

Accelerated design of polynomial multiplication for fully homomorphic encryption

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