This paper aims to improve the electrical properties of 50 V HVPMOS using the 0.35 μm 30_40_50 V BCD (bipolar-CMOS-DMOS) process by adjusting the dimensions of device structure without changing the original process. The process and device simulation of Silvaco Inc. has been used to analyze the influences of the channel length, overlap size, field oxide layer length and field plate length on the electrical properties of 50 V HVPMOS. The optimized dimensions were determined according to the simulation results, and feasibility of the optimization scheme was verified by the result of tape out. The test results show that the threshold voltage reduces to –0.98 V, the breakdown voltage increases to –68 V, the specific on-resistance is reduced by 13.5% and the saturation current is increased by 13.1% after the optimal design. Furthermore, the saturated zone is smoother without obvious kink effect.
ZOU Rong1, MIN Jia-hua1, CHU Chu2, LIANG Xiao-yan1, ZHANG Tao1, TENG Jia-qi1
. Electrical Properties Optimization of 50 V HVPMOS Based on 0.35 μm BCD Process[J]. Journal of Shanghai University, 2013
, 19(6)
: 567
-571
.
DOI: 10.3969/j.issn.1007-2861.2013.06.004
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