This paper proposes a hardware implementation scheme of SM4 and ZUC-256 ciphers. This scheme first provided hardware language description for the two ciphers, and then two reconfigurable units—reconfigurable register and reconfigurable S-box unit were constructed. Accordingly, based on the realization of two password algorithms, resource consumption was effectively reduced and resource utilization was improved. Hardware veri-fication was carried out using a field programmable gate array (FPGA). The results showed that the hardware overhead in the password reconfiguration scheme was significantly re-duced.