在控制器局域网（controller area network，CAN）总线通信中，位时序的处理关系到CAN能否正确地收发数据.基于总线标称位时间的周期结构及位同步的工作原理，提出CAN 2.0协议标称位时间的一种优化方法，即将传统的标称位时间由4个互不交叠的段简化成3个互不交叠的段，并在此基础上提出一种基于同步状态机的CAN总线位时序处理器的设计方法，提供可编程的时间段来补偿传播延迟时间和相位漂移，并对设计的电路进行仿真与验证.结果表明，相对于CAN协议规范标称位时间的4个互不交叠的段，减少了整个位时序处理过程使用的寄存器，简化了执行位同步的步骤，能更简便地处理CAN总线通信的位时序，实现了CAN总线协议中对位定时和位同步的控制，更好地优化了CAN网络的性能.

 The way in which the bit timing of controller area network (CAN) bus communication is dealt with determines whether the CAN controller can receive or transmit data correctly. This paper presents a structure of nominal bit time and the principle of bit synchronization. We give an optimized method of nominal bit time of CAN〖KG*1/9〗2.0 protocol that the four nonoverlapping segments of traditional nominal bit time is simplified to 3 nonoverlapping segments. Based on this, we propose a design method for bit timing processor （BTP） of CAN bus on the synchronized state machine. We also provide programmable time segments to compensate for the propagation delay times and phase shifts, and show simulation and verification of the design. The results show that the design in line with the CAN 2.0 protocol can more easily deal with the CAN bus communication bit timing. Control of CAN bus protocol on the bit timing and bit synchronization is realized, which better optimizes the CAN network.