提出了一种 SM4 和 ZUC-256 密码的硬件实现方案. 首先对两个密码算法进行硬件语言描述, 然后构建了两个可重构单元——可重构寄存器和可重构 S-box 单元, 从而在实现两个密码算法的基础上, 有效降低了资源消耗, 提高了资源利用率. 在现场可编程逻辑门阵列 (field programmable gate array, FPGA) 上进行硬件验证. 结果表明, 本密码可重构方案中的硬件开销有明显的降低.

This paper proposes a hardware implementation scheme of SM4 and ZUC-256 ciphers. This scheme first provided hardware language description for the two ciphers, and then two reconfigurable units—reconfigurable register and reconfigurable S-box unit were constructed. Accordingly, based on the realization of two password algorithms, resource consumption was effectively reduced and resource utilization was improved. Hardware veri-fication was carried out using a field programmable gate array (FPGA). The results showed that the hardware overhead in the password reconfiguration scheme was significantly re-duced.