收稿日期: 2018-03-09
网络出版日期: 2018-12-29
基金资助
国家自然科学基金研究项目(61376028);国家自然科学基金研究项目(61674100);上海市科委重大基础研究项目(16JC1400602)
A hardware accelerator for adaptive histogram equalization
Received date: 2018-03-09
Online published: 2018-12-29
针对动态直方图均衡 (dynamic histogram equalization, DHE) 算法处理效果不理想和算法应用不灵活的问题, 提出了一种基于改进型自适应直方图均衡化算法的现场可编程逻辑门阵列 (field programmable gate array, FPGA) 硬件加速器的设计方法. 该硬件加速器对直方图均衡化算法做了改进, 实现了自适应地限制对比度拉伸; 并且充分利用 FPGA 的并行体系架构和丰富的块存储资源的优点, 采用规则的模块化的设计方法完成了设计. 实验结果表明: 改进的算法不会产生过度增强、放大噪声、丢失图像细节的现象; 设计的硬件加速器在充分节约硬件资源的前提下能较好地满足实际应用的需求; 在实时图像处理中一帧图像的处理时间约为 0.1 ms, 使图像增强算法在图像实时处理中的应用更加灵活方便.
关键词： 现场可编程逻辑门阵列; 自适应; 直方图; 硬件加速器
陆申阳, 冉峰, 郭爱英, 沈华明 . 一种用于自适应直方图均衡化的硬件加速器[J]. 上海大学学报(自然科学版), 2020 , 26(3) : 401 -412 . DOI: 10.12066/j.issn.1007-2861.2044
In order to solve the problem that the dynamic histogram equalization (DHE) algorithm does not work well and that the algorithm cannot be applied flexibly, a field programmable gate array (FPGA)-based hardware accelerator design method for improved adaptive histogram equalization algorithm is proposed. The hardware accelerator improves the histogram equalization algorithm and adaptively limits the contrast stretch. It is designed in modularity after taking full advantage of the parallel architecture and abundant block storage resources that FPGA has. Experiment results show that the improved algorithm does not result in excessive enhancement, noise amplification and loss of image detail. The proposed hardware accelerator not only performs well in saving hardware resources but is effective as well in practical application. In real-time image processing, it takes only about 0.1 milliseconds for the processing of a frame image, thus making the image enhancement algorithm in real-time image processing more easily accessible.
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